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  • drexnx - Thursday, July 4, 2019 - link

    I'm honestly surprised all of the pure-play foundries haven't been doing this for years, seems like a no-brainer?
  • Hul8 - Thursday, July 4, 2019 - link

    Apart from the ever increasing ML in computing in general, maybe they have, but the public just hasn't heard about it? Samsung's fab arm is pushing hard to expand their market share; Trying to convince customers about their advantages through a PR campaign like this would fit in that.
  • Hul8 - Thursday, July 4, 2019 - link

    Note that the technology is available for 10 nm and down, with no mention of when it was first introduced. This news item is about extending supporting to 7 nm:

    > Synopsys has announced an *acceleration of development* on its yield learning platform designed to speed up ramp up of chips made using Samsung Foundry’s 7LPP (7 nm low power plus) process and newser technologies."
    (emphasis mine)

    Samsung may have been using it since 10 nm first debuted. The reason to make so much noise about it now could (again according to my speculation) be because customers are unsure about Samsung's 7 nm.
  • Smell This - Friday, July 5, 2019 - link


    Mmmm. Call me a skeptic but the *Yield Explorer* smells like the fanciful, ubiquitous (and dubious?) preemptive charts and graphs in the slide decks that proceeded the Chipzillah 14nm "Process-Architecture-Optimization (PAO)," or PAO+O+O+O.

    "The secure collaboration model using Yield Explorer has greatly helped us to work efficiently with key customers to achieve target production yields quickly. We look forward to expanding this cooperation with Synopsys as we ramp up production on our 5-nanometer technology node."

    Pretty much what *Hul8* said. I get that foundries want to optimize yields but bringing in 3rd-party 'consultants' can raise red flags.
  • zamroni - Friday, July 5, 2019 - link

    software simulation really helps chip development because transistor is basically analog device and 0-1 transition is actually not rectangular with 0s delay in analog signal
  • zamroni - Friday, July 5, 2019 - link

    chip fabrication is very chemical and nanophysic thing. it's not simple 0 or 1. simulation software really helps to tune many aspects of the fabrication.
  • Kevin G - Friday, July 5, 2019 - link

    I do wonder if the amount of time this took to appear on the market is based upon how long it’d take to validate the results during development. The datasets for the design are huge even for a small chip. Then simulated results generated in development have to be compared to the reality of a production run and reconciled. With a wafer taking several months to make it through a factory, that’s a good chunk of time just waiting for results. Silver lining is that the simulation could have occurred concurrently with the production run since the chip designers were not leveraging this as part of their development workflow.

    With this software looking to be extended to smaller nodes, I would hope that Samsung and Synopsys are working with a customer who is going to be entering risk production on those nodes. Real production data will be invaluable for everyone else using these tools afterward.
  • Teckk - Thursday, July 4, 2019 - link

    Every foundry l/IDM will have it some form and its details will be a pretty closely guarded piece of information. Yield will be the top priority especially with escalating costs as they try to go down towards lower nodes.
  • Ray Chen - Thursday, July 4, 2019 - link

    They have. Other foundries just don't use that "Yield Explorer" with a UI design from the 1990s.
  • Death666Angel - Thursday, July 4, 2019 - link

    Looks like every other solid lab program I've used. The "prettier" ones often have more bugs than these bare bones programs not designed to coddle the user.
  • surt - Thursday, July 4, 2019 - link

    Of course they have more bugs. Bugs are proportional to features. And those features exist because a product manager worked with users to find out what they need. You just aren't their target market.
  • FullmetalTitan - Friday, July 5, 2019 - link

    Customer engineers at a foundry might have limited access to these type of tools (such as simplified reporting tools, without as much detail), but the actual users are the failure analysis engineers, the process engineers looking for improvement targets, and the integration engineers trying to identify hidden weak points in layout or design rules. Not sure what Ray is basing his comment on, unless he has worked for multiple foundries.
  • Andrei Frumusanu - Thursday, July 4, 2019 - link

    The announcement isn't anything new, it's their new more aggressive focus.
  • Wardrop - Thursday, July 4, 2019 - link

    Now supporting Windows XP. Hooray
  • danjw - Friday, July 5, 2019 - link

    "process and newser technologies." I think you meant "newer".
  • SydneyBlue120d - Thursday, July 11, 2019 - link

    Can we expect better Exynos SOC then? :D

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