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  • FreckledTrout - Wednesday, August 26, 2020 - link

    So will Intel's SuperFin(lord I hate that name) and TSMC's approaches be similar?

    " 50% performance gain, up to 30% power reduction, and 1.7x density gain over N5" If that's the case then I can see why they are not moving to GAA-FET.
  • Arsenica - Wednesday, August 26, 2020 - link

    TSMC is targeting GAA for their 2 "nm" node.

    SuperFin is an awful name. They should have followed other foundries in re-naming their derivative nodes as if they were a different node (as GloFo's 14nm->12nm or TSMC's 10nm->7nm).

    Node "names" have for long lost any relation with the actual size of the transistors, so for marketing purposes it would have been more effective if Intel had re-named 10++ into 9nm or 8nm instead of SuperFin.

    At this rate Intel will be hyping their MegaRibbon 5nm while TSMC is talking marketing "picometers".
  • name99 - Wednesday, August 26, 2020 - link

    'TSMC is targeting GAA for their 2 "nm" node.'

    That's a strong statement. TSMC is happy to mix and match stable, tested technology with ONE new test item. (Think, eg, N7+ as a trial of EUV)

    I could imagine that if their current experimentation around GAA goes well, they might introduce an N3+ a year after N3 that is basically everything the same as N3 except using GAA (and presumably with GAA benefits, so some combination of lower power, slightly higher frequency or [of particular interest to AMD] the same high frequency as N3 but in rather smaller cells).
  • III-V - Wednesday, August 26, 2020 - link

    "That's a strong statement."

    I mean, that's not the first time it's been said either.
  • saratoga4 - Wednesday, August 26, 2020 - link

    I won't be at all surprised if they offer the 3nm BEOL with GAA and then call it "2nm", similar to how they did with 20nm and finfets.
  • astroboy888 - Thursday, August 27, 2020 - link

    TSMC 2nm will be a full node. Not an iteration of previous process. Brand new fabs are being built specifically for it.
  • hecksagon - Wednesday, August 26, 2020 - link

    "Most notably, Intel has mentioned that they will start using it within the next 5 years..."

    *Holds Breath*
  • Kamen Rider Blade - Wednesday, August 26, 2020 - link

    If they're going to come up with dumb names like "SuperFin" or "MegaRibbon".

    They should stick with 10nm+², or 10nm+³
  • name99 - Wednesday, August 26, 2020 - link

    Don't worry! Here's how this will play out.

    2022: Intel will announce how their 5nm UltraSheets are the best transistors ever! And they'll ship just as soon as those last pesky problems with 7nm are sorted out.
    2022: TSMC keeps their mouths shut as usual.
    2023: TSMC announces GAA sheets (just sheets, no branding nonsense) for 2nm
    2024: TSMC actually SHIPS 2nm GAA
    2026: Intel tells us that UltraSheets will ship any day now, just you wait, and they will be awesome, I tell you, even better than what we promised in 2022!!!
  • fallaha56 - Wednesday, August 26, 2020 - link

    ha yes, this forum really needs a like button lol
  • FreckledTrout - Wednesday, August 26, 2020 - link

    I truly hope you are wrong. We don't need AMD to become the new Intel. We need Intel back in the game by 2022 or so.
  • RedOnlyFan - Thursday, August 27, 2020 - link

    Why wait for 2022. September 2nd should be the date you should be counting on.
    Guessing tigerlake will rip the paintings.
  • Spunjji - Thursday, August 27, 2020 - link

    Yes, its brief period in the sun as the highest-performing quad-core mobile CPU and iGPU will totally make up for their continuing inability to release superior products in all their other markers 🙄
  • albertmamama - Wednesday, August 26, 2020 - link

    That will be bad for competition...
  • Spunjji - Thursday, August 27, 2020 - link

    Nailed it.
  • Santoval - Wednesday, August 26, 2020 - link

    There was an implied "or" between the "performance gain" and the "up to 30% power reduction" in that sentence that was left unstated, maybe because by now AnandTech readers in particular should well know that this is a case of "or", *never* (I'm referring to the period after 2005/2006, i.e. after Dennard scaling collapsed and Koomey's law started slowing down) of "and".
  • s.yu - Thursday, August 27, 2020 - link

    Yeah I've been expecting that it would be "or", but I still believe reportage should be accurate.
  • Spunjji - Thursday, August 27, 2020 - link

    I do feel like the "up to" indicates that it's a variable, but yes, being explicit does no harm.
  • kpaczari - Wednesday, August 26, 2020 - link

    typo:
    planar resistors to FinFET transistors -> planar transistors
  • ishould - Wednesday, August 26, 2020 - link

    At some point the industry is going to need to switch to pico-meter suffixes instead, if only to differentiate between "nodes". 3nm with finfet is going to be less dense than with gaafet, but 300pm with finfet and 250pm with gaafet makes it more clear
  • drexnx - Wednesday, August 26, 2020 - link

    wonder if they'll go to .x nanometer first like they did with micron before finally going to nanometer at the 90nm node. Back then it was weird to see something you'd always seen before as .13u == 130nm
  • Eliadbu - Wednesday, August 26, 2020 - link

    Back than the process name had something to do with the some of the transistor feature size, today it has nothing to do with with any size or density, So they can call the process unicorns and rainbows - not like
    x nm has to do more with the process.
  • Spunjji - Thursday, August 27, 2020 - link

    It really does have a lot to do with the density, though. The density has been improving at roughly the same rate as the name changes would imply.
  • Spunjji - Thursday, August 27, 2020 - link

    To be clear - the transistor sizes aren't accurately represented, but the differences between processes largely are. That seems to be the point of the exercise.
  • Arsenica - Wednesday, August 26, 2020 - link

    3 nm is 3000 pm.

    Angstroms would be a more marketable term ( 3 nm is 30 Å), but pretty much no component of a transistor would measure that as stochastics in that scale would kill the yields of anybody trying to actually reach Angstroms. Hell, stochastics are currently killing the yields of Intel's "copy-exact" methodology at 7 "nm".

    In a few years TSMC could likely announce their Å20 gate-all-around process featuring eh.. 15 nm gate ribbon/sheet widths.
  • FunBunny2 - Wednesday, August 26, 2020 - link

    in due time, these transistors with be Heisenberg devices, except not under humans' control.
  • quorm - Wednesday, August 26, 2020 - link

    0.3nm / 300 pm is unlikely to ever happen, unless the correspondence between node naming and transistor size becomes even less meaningful.
  • Slumberthud - Wednesday, August 26, 2020 - link

    Except that 3 nm is 3000 pm, not 300 pm.
  • astroboy888 - Thursday, August 27, 2020 - link

    Or angstrom. which is 1e-10. :) 1nm would be 10 angstrom.

    3nano-meter is 3000 pico-meter.
  • boeush - Friday, August 28, 2020 - link

    Keep in mind that the diameter of a single Silicon atom is 0.222 nm (at room temperature, I believe) - which is 222 pm. Thus it's physically impossible for a transistor to be smaller than that, at least.

    Worse, if one considers the Si crystal lattice, then a single unit of the cubic lattice is about 0.543 nm on its side. This is probably the irreducible size quantum for Si-based circuitry, since at fractions of this you might wind up with a chemically-unstable structure.

    But in reality, it's unlikely that transistors will ever shrink to the size of a single Si atom, or even a single unit of Si crystal lattice. If one assumes let's say 3 lattice units in terms of nanowire/nanosheet width for end-state transistor tech, then the absolute size limit for the 'smallest feature' would be around 1.63 nm or so. It's probably safe to assume anything beyond that would be solidly in the realm of fantasy.

    Of course, 'smallest feature' in this case will have little in common with the size of an actual transistor (including any spacing required between it and adjacent transitors to suppress electromagnetic cross-talk.)
  • RedOnlyFan - Thursday, August 27, 2020 - link

    What does tsmc actually mean when they market "5nm" or "2nm", transistor gate lengths?
    How are they doing "5nm" or "2nm" with DUV?
    How many layers euv are they using.. That should be confidential.. Any guesses?
    Ian maybe you can enlighten us here.
  • edzieba - Thursday, August 27, 2020 - link

    The big three scaling technologies as we enter the single-digit-nm realm are:
    - EUV for patterning with reduced numbe rof multi-paterning steps (EUV multi-patterning will rear its head soon enough though)
    - Cobalt as a replacement for Copper in lower metal layers (and ascending to higher layers as scales reduce)
    - Switching from monolithic fins to perforated things (nanowires/nanosheets).

    Intel started by tackling Cobalt first and leaving others to work the bugs out of EUV (mainly isues with the masks and pellicles, as yet unresolved and mostly worked around by significantly reducing the mask life). TSMC and Samsung aimed at EUV first, with TSMC being more gung-ho about getting /some/ EUV in their process even if only for the lowest hanging fruit and Samsung still more tentative. As scales reduce, Intel will need to scale up EUV, and TSMC & Samsung will need to get Cobalt (or another metal, but Cobalt is the least-worst option) into their metal layers, and everyone will need new gate topologies. How well they do getting everything together depends on how much knowledge transfer occurs: Intel may bizzarely be best placed here. They expected EUV to be as hard to implement as it has turned out to be, but expected Cobalt to be much easier than it turned out to be. However, resolving EUV issues is less down to the fabs themselves, and more by ASML and other suppliers who will happily sell solutions to Intel as they do everyone else. But the solutions to getting Cobalt onto the dies reliably and dealing with differential thermal expansion (as killed the 'original' 10nm) remain sitting inside the heads of Intel engineers at the moment.
  • Tomatotech - Thursday, August 27, 2020 - link

    PlanarFET, yes, it's layering. FinFET, yes, make it via more layering. GAAFET.... eh how do they physically make it? Does each nanowire involve stages of laying down material, then laying down the wire, then laying down more material, then laying down another wire on top?

    Suddenly a transistor has gone from maybe 3 layer to maybe 30+ layers of material, or am I getting the manufacturing process completely wrong?
  • Spunjji - Thursday, August 27, 2020 - link

    I'd really like an explainer on this, too!
  • edzieba - Thursday, August 27, 2020 - link

    The 'layers' that will eventually form the wires/ribbons are laid down, a 'fin' is etched, and then additional etching 'side cuts' the gaps between the layers to leave the wires/ribbons, which are than filled in as the gate is deposited.
  • lukedotlol - Tuesday, September 8, 2020 - link

    Interesting Gate-All-Around chip recently filed for patent
    by IBM https://uspto.report/patent/app/20200266060
  • Oberoth - Wednesday, December 16, 2020 - link

    Any update to this?
    I wonder if there is any chance that Intel's GAA team is totally separate and could mean it will be ready much faster (ie on time) than waiting for 10nm to work properly then waiting for 7nm to working properly then in a few years after that bringing it to market?

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